This invention relates generally to arrangements for protecting the data integrity of memory devices. More specifically, this invention pertains to a protection arrangement suitable for large arrays of battery backed-up CMOS Random Access Memories (RAMs).
In systems having large arrays of RAMs, the data stored within the RAMs are generally protected from a power-down of the RAM itself by a battery back-up scheme. Such battery back-up schemes maintain power to the RAM even when power to the rest of the system is interrupted.
However, even though power to the RAMs is maintained, a power interruption to the rest of the system can compromise data integrity. Specifically the data integrity of CMOS RAMs, such as in microprocessor systems can be compromised by spurious write and chip select commands applied to a RAM such as a chip enable of short time duration, i.e., an enable signal having a time duration that doesn't meet design standards when power to control circuits is applied and removed. The data integrity of a RAM is also compromised when the voltage at any pin of a CMOS RAM rises above a designated V.sub.cc supply voltage due to power supply differentials.
When only one or two CMOS RAMs are used in a microprocessor-based system and the frequency of writing into the RAMS is relatively low, the problem of data integrity being compromised by spurious writes and chip selects can be dealt with easily. A simple voltage comparator is coupled to a chip enable line on each RAM to determine when the supply voltage drops below a predetermined "safe" level. Power for each CMOS RAM is derived from a logic supply using a low voltage drop Schottky diode to minimize voltage drop. Such an arrangement is shown in FIG. 1.
Referring now to FIG. 1, there is shown a typical memory protection circuit for a battery backed-up CMOS RAM. Values shown on FIG. 1 are typical for CMOS technology. For other technologies, the values would have to be altered so as to be consistent with the different voltage and logic levels required.
A CMOS RAM 10 has its V.sub.cc supply battery backed-up by a battery 12 and a battery charging resistor 14. V.sub.cc power for CMOS RAM 10 is derived from a primary power supply (typically five volts) via a Schottky diode 16 and is coupled to the V.sub.cc input of RAM 10. In addition, power from the primary power supply is coupled through Schottky diode 16 and a charging resistor 14 to charge battery 12. A particular RAM 10 is selected by a user control system (not shown) for a write or read operation via an address signal generated on an address bus 18. The address information on bus 18 is decoded by an address decoder 20. The chip enable output 22 of address decoder 20 corresponding to, and thereby specifying, RAM 10 is coupled to one of the RAM's chip enable inputs 32. A second chip enable input 24 of RAM 10 is coupled to the output of a comparator 26.
Comparator circuit 44 including a comparator 26 compares the voltage of the primary supply, coupled to its inverting input, with a threshold voltage established by current flowing from a bulk power supply (not shown) through a resistor 28 and a Zener diode 30. For CMOS technology, Zener diode 30 is typically 4.8 volts. Of course, for other technologies, Zener diode 30 would have a different value.
If the voltage from the primary power supply drops below 4.8 volts, as established by Zener diode 30, then a logic level "high" signal appears at the output of comparator 26 and is coupled to chip enable 24 of RAM 10. This prevents the writing into RAM 10 since all chip enables must be low for writing to take place. Thus, during a power interruption, as soon as the primary power supply voltage drops below 4.8 volts, it becomes impossible to write into RAM 10.
The protection arrangement shown in FIG. 1, however, is not fail safe and has several operational disadvantages. One such disadvantage is that its application is limited to RAMs having two separate and distinct chip enable inputs. Also, the arrangement requires a low voltage drop Schottky diode in the power supply. If the voltage drop across this diode is too great, the CMOS RAM may not operate because its power supply voltage is too low or it may latch up because the voltage on its input pins exceeds the voltage on its V.sub.cc supply pin. Another disadvantage with this simple arrangement is that the integrity of the writing operation is not protected if power fails during a write access. During such a power failure, data may or may not be written into RAM 10. Yet another disadvantage with the simple circuit arrangement shown in FIG. 1 is that many CMOS RAM devices 10 do not tolerate a chip enable signal of less than a predetermined duration of time (short chip enable) such as can occur during a power interruption. Also the arrangement requires close tolerances on the supply to the other circuit logic (not shown) and on the V.sub.cc supply for RAMs 10.
Referring now to FIG. 2, there is shown a schematic diagram of another known memory protection circuit that is utilized when the simple arrangement of FIG. 1 is inadequate. The FIG. 2 arrangement has been used when larger arrays of RAMs are used, when writing operations occur more frequently or are more likely to occur during a power failure, and when RAMS having only a single chip enable are used.
In this second known arrangement, the address decoded chip enable (CE) to each RAM (only one of which is shown) is latched on each memory cycle and buffered. The latching prevents short chip enables and their attendant possible loss of data. The buffers are disabled after the last processor cycle is completed. Power is typically taken from the logic supply or derived from a zener regulation circuit. Specifically, the address decoded chip enable signal 22 from address decoder 20 is latched by a latch 60 and is then buffered by a three-state buffer 62. A comparator circuit 50, analogous to comparator circuit 44 shown in the FIG. 1 arrangement, includes a comparator 52, Zener diode 54, and resistor 56 for establishing a threshold voltage and accompanying that threshold voltage with that of the primary power supply. Comparator circuit 50 disables RAM 10 when the voltage from the primary power supply drops below 4.8 volts.
In this FIG. 2 arrangement, the latching of the chip enable for each of RAMs 10 prevents a short chip enable signal from being coupled to a RAM and the possible loss of data resulting therefrom. Buffer 62 is disabled after each processor cycle is completed. A time delay element 58 helps to prevent a short time duration chip enable by delaying removal of the enable signal for a given time period until the external circuitry, such as a microprocessor, has been reset (by circuitry not shown). Power for the protection circuit is typically either taken from the logic supply or derived from a simple Zener regulator circuit.
The arrangement shown in FIG. 2 also has operational disadvantages. Using the circuit arrangement of FIG. 2, each RAM 10 (only one shown in the Figure) requires a separate latch 60 and buffer 62. It also rquires close tolerances on the V.sub.cc supply to other circuit logic (not shown) and on the Zener diode supply for RAMs 10. Also, there is a danger of disabling the RAM 10 chip enable line during a read or write operation.